Silly stupid experiment. How expensive is to add two numbers in Verilog? How expensive is subtracting? Multiplying? Shifting?

Not finding any definite answer, I tried myself and synthesized some common stuff using Quartus and Verilog to see the results myself. Target FPGA is a Cyclone V 5CSEMA4U23C6 from an Atlas development board.

Circuit ALMs Regs Memory bits Max. Freq.
Register-Register copy 8->8 5 16 0 605.33 MHz
8x8 Adder 9 24 0 205.09 MHz
8x8 Adder (with carry) 9 25 0 219.49 MHz
16x16 Adder 17 48 0 192.75 MHz
32x32 Adder 33 96 0 116.93 MHz
Bit shift register (8 bit) 3 9 0  623.44 MHz
Bit shift register (1024 bit) 16 26 1023 227.12 MHz
Byte shift register (2 byte) 7 24 0 603.86 MHz
Byte shift register (128 byte) 7 24 1016 246.79 MHz
8x8 -> 16 Multiplier * 1 0 0 310.08 MHz
16x16 -> 32 Multiplier * 1 0 0 310.08 MHz

* Uses a DSP block out of a total of 84 DSP blocks.

Funny results, seems like Multiply is consistently faster than the simplest addition as long as you have enough DSP (Multiply-Accumulate?) blocks.